DSD DMR and ETSI TS 102 361 confusion

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mryamac

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Jul 17, 2017
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Hello,
I m new at these subject, so I started to read DSD source code. I found that DSD source code and ETSI TS 102 361 are not match. Here what is confusing for me:

ETSI TS 102 361 (European DMR Standard)

This document says that length of the sync bits are 48.

DSD source code:
There are some constant in dsd.h file and it says that sync pattern of the DMR like this:

#define DMR_BS_DATA_SYNC "313333111331131131331131"
#define DMR_BS_VOICE_SYNC "131111333113313313113313"
#define DMR_MS_DATA_SYNC "311131133313133331131113"
#define DMR_MS_VOICE_SYNC "133313311131311113313331"

Also these bits are not match with ETSI TS 102 361 document.
Sync pattern according to the document:

BS
sourced
Voice
Hex 7 5 5 F D 7 D F 7 5 F 7
Binary 0111 0101 0101 1111 1101 0111 1101 1111 0111 0101 1111 0111
Data
Hex D F F 5 7 D 7 5 D F 5 D
Binary 1101 1111 1111 0101 0111 1101 0111 0101 1101 1111 0101 1101
MS
sourced
Voice
Hex 7 F 7 D 5 D D 5 7 D F D
Binary 0111 1111 0111 1101 0101 1101 1101 0101 0111 1101 1111 1101
Data
Hex D 5 D 7 F 7 7 F D 7 5 7
Binary 1101 0101 1101 0111 1111 0111 0111 1111 1101 0111 0101 0111
RC
sync
Hex 7 7 D 5 5 F 7 D F D 7 7
Binary 0111 0111 1101 0101 0101 1111 0111 1101 1111 1101 0111 0111
TDMA
direct mode time
slot
1
Voice
Hex 5 D 5 7 7 F 7 7 5 7 F F
Binary 0101 1101 0101 0111 0111 1111 0111 0111 0101 0111 1111 1111
Data
Hex F 7 F D D 5 D D F D 5 5
Binary 1111 0111 1111 1101 1101 0101 1101 1101 1111 1101 0101 0101
TDMA
direct mode time
slot
2
Voice
Hex 7 D F F D 5 F 5 5 D 5 F
Binary 0111 1101 1111 1111 1101 0101 1111 0101 0101 1101 0101 1111
Data
Hex D 7 5 5 7 F 5 F F 7 F 5
Binary 1101 0111 0101 0101 0111 1111 0101 1111 1111 0111 1111 0101
Reserved
SYNC
pattern
(See note)
Hex D D 7 F F 5 D 7 5 7 D D
Binary 1101 1101 0111 1111 1111 0101 1101 0111 0101 0111 1101 1101
 

trashbag

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Joined
May 13, 2017
Messages
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For DMR_BS_DATA_SYNC:

1 = 01
3 = 11

Code:
3 1 3 3 3 3 1 1 1 3 3 1 1 3 1 1 3 1 3 3 1 1 3 1
110111111111010101111101011101011101111101011101
D   F   F   5   7   D   7   5   D   F   5   D‬
This is done in dmr_data.c:

Code:
sync[i] = (dibit | 1) + 48;
But it is a bit confusing since this representation doesn't quite match the dibit mapping from ETSI doc, table 10.3.

Regards
 
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