Hi, everyone I had a problem with micro phase ant sdr e200 so I have my own custom fpga design which is made from scratch not followed any reference desin , my issue here is that after generating the bit file of my design....I am using pynq framework for the board my problem here is iam using the files given in their github repo, the dtb file, uboot , fsbl etc and even the bin file they gave which they told would help in bridging the gap of PL side ethernet in the e200 .
But everytime I uplooad my bitstream by replacing the refernce bitstream present in the bin file the board goes to sleep mode, whihc might be because the fsbl and uboot i smade according to that design but when I generate a bin file using my
But everytime I uplooad my bitstream by replacing the refernce bitstream present in the bin file the board goes to sleep mode, whihc might be because the fsbl and uboot i smade according to that design but when I generate a bin file using my
