DSD FSK Modulation missing part

[mryamac]

Hello All,
My question is about DSD source code. I was inspecting dsd_frame_syn.c file and I found that symbol is converted to bits with some missing part. It only converts to the 01 and 11. There must be some if else statement so we can get all combination (00,01,10,11). Other bits can be found using some threshold value. If anyone calculate this threshold and share how the calculation can be done, it is very helpful. Thanks all.

Here is the code:

//determine dibit state
if (symbol > 0)
{
*state->dibit_buf_p = 1;
state->dibit_buf_p++;
dibit = 49; // '1'
}
else
{
*state->dibit_buf_p = 3;
state->dibit_buf_p++;
dibit = 51; // '3'
}

 

[slicerwizard]

The code that finds frame sync patterns assumes that those patterns are simple two level signals (which is actually not true in all cases), so it only does a simple (too simple, IMO) "is the value positive or negative?" check to determine each symbol value ("1" or "3"); those values are appended and tested for matches against known sync patterns.

If you want code that builds dibits, don't look in the sync pattern logic. Look in the dibit builder...