The following is a cut & paste of two emails in the SDR-Radio-com Yahoo! group this morning.
Airspy HF+
Preliminary specs:
RX range: 0 .. 30 MHz (HF) and 60 - 270 MHz (+)
Architecture: Hybrid (Direct conversion + DDC) using 2 x sigma delta ADC's @ 36MSPS
Front end: Tracking Filters (all bands), High Dynamic Range LNA's and Mixers
AGC: Smart AGC controlled by the DSP
DSP: CIC, CFIR and a final (programmable) channel FIR - 18bit resolution
Final bandwidth/resolution after DDC: 18bit @ 600kHz - Scaled and streamed as 16bit
Image rejection: better than 120dBc
Blocking DR: 108 dB
Separate HF and VHF RF inputs - with option to use one multiplexed input if desired
USB 2.0 with Plug and play - No drivers needed
The RF section resides inside a metal shield
Aluminium enclosure about 60 x 100 x 15 mm^3
2 x 36MSPS IQ (equivalent to direct sampling at 72 MSPS) gives roughly 36MHz of bandwidth, however the ADC's used are sigma-delta with intrinsic anti-alias filtering.
We start with 16bit IQ at 36MSPS then it is frequency translated and decimated to 744.192 ksps 18bit IQ with a bit more than 600 kHz bandwidth plus the digital filter roll off. Given the very nature of sigma delta ADC's, the pressure on the front-end filtering is relaxed and the tracking filters are even more effective.
The image rejection is performed using a newly designed algorithm that matches the performance of the hardware.
All the decimation number crunching happens in the device like in most high end DDC receivers, so we only need a small USB throughput in the end (~23Mbps), and the CPU usage in the PC is very low.
Performance wise, the result is comparable to things like Perseus, RFSPACE, Elad, etc. but with a more modern full CMOS sensitive front end and at a fraction of the price.
Airspy HF+
Preliminary specs:
RX range: 0 .. 30 MHz (HF) and 60 - 270 MHz (+)
Architecture: Hybrid (Direct conversion + DDC) using 2 x sigma delta ADC's @ 36MSPS
Front end: Tracking Filters (all bands), High Dynamic Range LNA's and Mixers
AGC: Smart AGC controlled by the DSP
DSP: CIC, CFIR and a final (programmable) channel FIR - 18bit resolution
Final bandwidth/resolution after DDC: 18bit @ 600kHz - Scaled and streamed as 16bit
Image rejection: better than 120dBc
Blocking DR: 108 dB
Separate HF and VHF RF inputs - with option to use one multiplexed input if desired
USB 2.0 with Plug and play - No drivers needed
The RF section resides inside a metal shield
Aluminium enclosure about 60 x 100 x 15 mm^3
2 x 36MSPS IQ (equivalent to direct sampling at 72 MSPS) gives roughly 36MHz of bandwidth, however the ADC's used are sigma-delta with intrinsic anti-alias filtering.
We start with 16bit IQ at 36MSPS then it is frequency translated and decimated to 744.192 ksps 18bit IQ with a bit more than 600 kHz bandwidth plus the digital filter roll off. Given the very nature of sigma delta ADC's, the pressure on the front-end filtering is relaxed and the tracking filters are even more effective.
The image rejection is performed using a newly designed algorithm that matches the performance of the hardware.
All the decimation number crunching happens in the device like in most high end DDC receivers, so we only need a small USB throughput in the end (~23Mbps), and the CPU usage in the PC is very low.
Performance wise, the result is comparable to things like Perseus, RFSPACE, Elad, etc. but with a more modern full CMOS sensitive front end and at a fraction of the price.
